ADE3000SX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ADE3000SX Datasheet PDF : 88 Pages
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ADE3XXX
Register Name
OMUX_ DLY_GB4
OMUX_ DLY_GB6
OMUX_ DLY_RB0
OMUX_ DLY_RB2
OMUX_ DLY_R_B4
OMUX_ DLY_R_B6
OMUX_ DLY_TCON_0
OMUX_ DLY_TCON_2
OMUX_ DLY_TCON_4
OMUX_ DLY_TCON_6
OMUX_ DLY_VS_ENAB
OMUX_ DLY_CLK_HS
OMUX_CTRL_3
OMUX_REFCOUNT
Pulse Width Modulation (PWM) Block
Table 29: Output Mux Registers (Sheet 3 of 3)
Addr
0x0C3E
0x0C3D
0x0C3C
0x0C3B
0x0C3A
0x0C39
0x0C38
0x0C37
0x0C36
0x0C35
0x0C34
0x0C33
0x0C51
0x0C52
Mode Bits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:3]
[2]
[1]
[0]
[7:6]
R
[5:0]
Default
Description
0x0
Delay for OGB5
0x0
Delay for OGB4
0x0
Delay for OGB7
0x0
Delay for OGB6
0x0
Delay for ORB1
0x0
Delay for ORB0
0x0
Delay for ORB3
0x0
Delay for ORB2
0x0
Delay for ORB5
0x0
Delay for ORB4
0x0
Delay for ORB7
0x0
Delay for ORB6
0x0
Delay for TCON1
0x0
Delay for TCON0
0x0
Delay for TCON3
0x0
Delay for TCON2
0x0
Delay for TCON5
0x0
Delay for TCON4
0x0
Delay for TCON7
0x0
Delay for TCON6
0x0
Delay for VSYNC
0x0
Delay for ENAB
0x0
Delay for CLK
0x0
Delay for HSYNC
Reserved
0x0
PWM mux mode
0x0
PWM enable
0x0
TCON data invert enable, with computed
data invert pin.
Reserved
0x0
returns a value that indicates the ADE gate
speed -- a function of temp and voltage
higher = faster logic
2.24
Pulse Width Modulation (PWM) Block
The PWM B block generates two signals to control backlight inverter switching power components
directly. It is derived from XCLK and powered up independently of the DOTCLK and INCLK
domains. Frequency, duty cycle, polarity and overlap/non-overlap are programmable. The output
frequency can “free-run” or lock to output vsync.
77/88
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