ADP-I2C-USB-Z View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP-I2C-USB-Z Datasheet PDF : 108 Pages
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Data Sheet
ADP1051
PWM OUTPUTS (OUTA, OUTB, OUTC, OUTD, SR1,
AND SR2)
The PWM outputs are used for control of the primary side drivers
and the synchronous rectifier drivers. They can be used for several
topologies, such as hard-switched full bridge, zero-voltage-switched
full bridge, phase shifted full bridge, half bridge, push pull, two-
switch forward, active clamp forward, interleaved buck, and
others. Delays between rising and falling edges can be individually
programmed. Special care must be taken to avoid shootthrough and
cross conduction. It is recommended that the ADP1051 GUI soft-
ware be used to program these outputs. Figure 12 shows an example
configuration to drive a zero-voltage-switched full bridge topology
with synchronous rectification. The QA, QB, QC, QD, QSR1, and
QSR2 switches are driven separately by the PWM outputs (OUTA,
OUTB, OUTC, OUTD, SR1, and SR2). Figure 13 shows an example
of PWM settings for the power stage shown in Figure 12.
The PWM and SRx outputs are all synchronized with each other.
Therefore, when reprogramming more than one of these outputs,
it is important to first update all of the registers and then latch the
information into the shadow registers at one time. During the
reprogramming operation, the outputs are temporarily disabled. To
ensure that new PWM timings and the switching frequency setting
are programmed simultaneously, a special instruction is sent to
the ADP1051 by setting Register 0xFE61[2:1] (the GO commands).
It is recommended that the PWM outputs not in use be disabled via
Register 0xFE53[5:0].
VIN
QA
QC
See the PWM Outputs Timing Registers section for additional
information about the PWM timings.
SYNCHRONOUS RECTIFICATION
SR1 and SR2 are recommended for use as the PWM control signals
when synchronous rectification is in use. These PWM signals can
be configured much like the other PWM outputs.
An optional soft start can be applied to the synchronous rectifier
(SR) PWM outputs. The SR soft start can be programmed using
Register 0xFE08[4:0].
When the SR soft start is disabled (Register 0xFE08[1:0] = 00), the
SR signals are immediately turned on to their modulated PWM
duty cycle values.
When the SR soft start is enabled (Register 0xFE08[1:0] = 11), the
SR1 and SR2 rising edges move left from the tRx + tMODU_LIMIT position
to the tRx + tMODULATION position in steps that are set in Register
0xFE08[3:2]. tRx represents the rising edge timing of SR1 (tR5) and
the rising edge timing of SR2 (tR6) (see Figure 68); tMODU_LIMIT
represents the modulation limit defined in Register 0xFE3C (see
Figure 67); tMODULATION represents the real-time modulation value.
The SR soft start is still applicable even if the SR1 and SR2 are not
programmed to be modulated. When the SR soft start is enabled,
the SR1 and SR2 rising edges move left from the tRx + tMODU_LIMIT
position to the tRx position in steps that are set in Register
0xFE08[3:2].
QB
QD
QSR1
QSR2
DRIVER
SR1 SR2
DRIVER
ISOLATOR
OUTA
OUTB
OUTC
OUTD
Figure 12. PWM Assignment for Zero-Voltage-Switched Full Bridge Topology with Synchronous Rectification
Figure 13. PWM Settings for Zero-Voltage-Switched Full Bridge Topology with Synchronous Rectification Using the ADP1051 GUI
Rev. B | Page 15 of 108
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