ADP-I2C-USB-Z View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP-I2C-USB-Z Datasheet PDF : 108 Pages
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ADP1051
Voltage Feedback Sensing (VS+, VS− Pins)
The VS sense point on the power rail requires an external resistor
divider (R1 and R2 in Figure 20) to bring the nominal differential
mode signal to 1 V between the VS+ and VS− pins (see Figure 20).
This external resistor divider is necessary because the VS ADC
input range of the ADP1051 is 0 V to 1.6 V. When R1 and R2 are
known, the VOUT_SCALE_LOOP parameter can be calculated
using the following equation:
VOUT_SCALE_LOOP = R2/(R1 + R2)
In a 12 V system with resistor dividers of 11 kΩ and 1 kΩ, the
VOUT_SCALE_LOOP can be calculated as follows:
VOUT_SCALE_LOOP = 1 kΩ/(11 kΩ + 1 kΩ) = 0.08333
LOAD
ADP1051
DIGITAL
COMPENSATOR
VOLTAGE SENSE
REGISTERS
HIGH SPEED
ADC
ACCURATE
ADC
VS+ R1
VS– R2
VOUT_UV_FAULT FLAG
VOUT_UV_ FAULT_LIMIT
Figure 20. Voltage Sense Configuration
Voltage Sense ADCs
Two kinds of sigma-delta (Σ-Δ) ADCs are used in the ADP1051
feedback loop, as follows:
Low frequency (LF) ADC, running at 1.56 MHz
High frequency (HF) ADC, running at 25 MHz
The Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution that is
obtained depends on how long the output bit stream of the Σ-Δ
ADC is filtered.
The Σ-Δ ADCs also differ from Nyquist rate ADCs in that the
quantization noise is not uniform across the frequency spectrum.
At lower frequencies, the noise decreases. At higher frequencies,
the noise increases (see Figure 21).
NYQUIST ADC
NOISE
Σ-Δ ADC
NOISE
FREQUENCY
Figure 21. ADC Noise Performance
Data Sheet
The low frequency ADC runs at approximately 1.56 MHz. For
a specified bandwidth, the equivalent resolution is calculated as
ln(1.56 MHz/BW)/ln(2) = N bits
For example, at a bandwidth of 95 Hz, the equivalent resolution/
noise is
ln(1.56 MHz/95 Hz)/ln(2) = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 MHz/1.5 kHz)/ln(2) = 10 bits
The high frequency ADC has a 25 MHz clock. It is comb filtered and
outputs at the switching frequency into the digital compensator. See
Table 5 for equivalent resolution at selected sampling frequencies.
Table 5. Equivalent Resolutions for High Frequency ADC
at Selected Switching Frequencies
fSW (kHz)
High Frequency ADC Resolution (Bits)
49 to 87
9
97.5 to 184
8
195.5 to 379 7
390.5 to 625 6
The high frequency ADC has a range of ±25 mV. Using a base
switching frequency of 97.5 kHz at an 8-bit HF ADC resolution,
the quantization noise is 0.195 mV (1 LSB = 2 × 25 mV/28 =
0.195 mV). When the switching frequency increases to 195.5 kHz
at a 7-bit HF ADC resolution, the quantization noise is 0.391 mV
(1 LSB = 2 × 25 mV/27 = 0.391 mV). Increasing the switching
frequency to 390.5 kHz increases the quantization noise to 0.781 mV
(1 LSB = 2 × 25 mV/26 = 0.781 mV).
Output Voltage Adjustment Commands
In the ADP1051, the voltage data for commanding or reading
the output voltage or related parameters is in linear data format.
The linear format exponent is fixed at −10 decimal (see the
VOUT_MODE command, Register 0x20, in Table 21).
The following three basic commands are used for setting the
output voltage:
VOUT_COMMAND command (Register 0x21, Table 22)
VOUT_MARGIN_HIGH command (Register 0x25, Table 26)
VOUT_MARGIN_LOW command (Register 0x26, Table 27)
One of these three values is selected by the OPERATION command
(Register 0x01, Table 13).
The VOUT_MAX command (Register 0x24, Table 25) sets an
upper limit on the output voltage that the ADP1051 can command,
regardless of any other commands or combinations.
During output voltage adjustment, use the VOUT_TRANSITION_
RATE command (Register 0x27, Table 28) to set the rate (in mV/µs)
at which the VS± pins change voltage.
Rev. B | Page 20 of 108
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