ADP-I2C-USB-Z View Datasheet(PDF) - Analog Devices
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Description
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ADP-I2C-USB-Z Datasheet PDF : 108 Pages
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ADP1051
Data Sheet
the phase of the external clock signal. The ADP1051 detects the
phase shift between the external clock signal and the internal clock
signal when synchronization is enabled. When the phase shift falls
within the phase capture range, synchronization begins.
The ADP1051 synchronizes to the external clock frequency as
follows:
1. The synchronization function is enabled by Register 0xFE12[3]
and Register 0xFE12[0], and the ADP1051 starts to detect the
period of the external clock signal applied at the SYNI/FLGI pin.
2. If all the periods of the consecutive 64 most recent cycles of the
external clocks fall within 90% to 110% of the internal switching
clock period, the ADP1051 uses the latest current cycle as the
synchronization reference, and the period of the external clock
is identified. This interval is t2 or t4, as shown in Figure 17.
Otherwise, the ADP1051 discards this cycle and looks for the
next cycle (frequency capture mode).
3. After the external clock period is determined, the ADP1051
detects the phase shift between the external clock (plus the delay
time set by Register 0xFE11) and the internal PWM signal. If
the phase shift is within the phase capture range, the internal
and external clocks are synchronized (phase capture mode).
4. At this point, the PWM clock is synchronized with the external
clock. Cycle-by-cycle synchronization starts.
5. If the external clock signal is lost at any time, or if the period
exceeds the minimum limit (89% of the internal programmed
frequency) or the maximum limit (114% of the internal
programmed frequency), the ADP1051 takes the last valid
external clock signal as the synchronization reference source.
At the same time, the phase shift between the synchronization
reference and the internal clock is detected. When the phase
shift falls within the phase capture range, the PWM clock
returns to the internal clock set by the internal oscillator.
This interval is t1 or t3, as shown in Figure 17.
This is the first synchronization unlock condition, called
Synchronization Unlocked Mode 1, in which the switching
frequency is out of range (range is 89% to approximately 114%
of the internal programmed frequency).
6. If the period of the external SYNI signal changes significantly
(for example, if the period difference between contiguous cycles
exceeds 280 ns), the ADP1051 takes the last valid external
clock signal as the synchronization reference source. At the
same time, the phase shift between the synchronization
reference and the internal clock is detected. When the phase
shift falls within the phase capture range, the PWM clock
returns to the internal clock set by the internal oscillator.
This is the second synchronization unlock condition, called
Synchronization Unlocked Mode 2, in which the phase shift
exceeds 280 ns.
Figure 17 shows the synchronous operation diagram. The internal
frequency, fSW_INT, is the internal free-running frequency of the
ADP1051. Before the synchronization is locked, the ADP1051
runs at fSW_INT. The external frequency, fSW_EXT, is the frequency of
the external clock that the ADP1051 needs to synchronize. After
synchronization is locked, the ADP1051 runs at fSW_EXT.
The ADP1051 does not allow the switching frequency to run across
the boundaries of 97.5 kHz, 195.5 kHz, or 390.5 kHz on the fly.
Ensure that the external clock does not run across these boundaries.
Otherwise, the internal switching frequency cannot be set within
±10% of these boundaries.
EXTERNAL CLOCK FREQUENCY
INTERNAL CLOCK FREQUENCY
fSW
OPERATING SWITCHING FREQUENCY
t1
t2
t3
t4
114% fSW_INT
110% fSW_INT
fSW_INT
90% fSW_INT
89% fSW_INT
UNIT
ON
UNIT UNIT
OFF ON
Figure 17. Synchronization Operation
TIME
Rev. B | Page 18 of 108
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