ADP-I2C-USB-Z View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP-I2C-USB-Z Datasheet PDF : 108 Pages
| |||
ADP1051
Data Sheet
The advantage of the SR soft start is that it minimizes the output
voltage undershoot that occurs when the SR FETs are turned on
without a soft start. The advantage of turning the SRx signals
completely on immediately is that they can help minimize the
voltage transient caused during a load step.
Using Register 0xFE08[4], the SR soft start can be programmed to
occur only once (the first time that the SRx signals are enabled) or
every time that the SRx signals are enabled (for example, when
the system enters or exits deep light load mode).
When programming the ADP1051 to use the SR soft start, ensure
the correct operation of this function by setting the falling edge of
SR1 (tF5) to a lower value than the rising edge of SR1 (tR5) and setting
the falling edge of SR2 (tF6) to a lower value than the rising edge of
SR2 (tR6). During the SR soft start, the rising edges of SRx move
gradually from the right side (the tRx + tMODU_LIMIT position) to the
left side to increase the duty cycle.
The ADP1051 is well suited for dc-to-dc converters in isolated
topologies. Every time a PWM signal crosses the isolation barrier,
a propagation delay is added because of the isolating components.
Using Register 0xFE3A[5:0], an adjustable delay (0 ns to 315 ns in
steps of 5 ns) can be programmed to move both SR1 and SR2 later
in time to compensate for the added propagation delay. In this way,
all the PWM edges can be aligned (see Figure 68).
PWM MODULATION LIMIT AND 180° PHASE SHIFT
The modulation limit register (Register 0xFE3C) can be programmed
to apply a maximum modulation limit to any PWM signal, thus
limiting the modulation range of any PWM output. If modulation
is enabled, the maximum modulation limit is applied to all PWM
outputs collectively. This limit, t , MODU_LIMIT is the maximum time
variation for the modulated edges from the default timing, following
the configured modulation direction (see Figure 14). There is no
setting for the minimum duty cycle limit. Therefore, the user must
set the rising edges and falling edges based on the case with the least
modulation.
OUTX
tRX
tFX
tMODU_LIMIT
OUTY
t0
tMODU_LIMIT
tRY
tFY
tS/2
tS
3tS/2
Figure 14. Setting Modulation Limits
Each least significant bit (LSB) in Register 0xFE3C corresponds to
a different time step size, depending on the switching frequency
(see Table 152). If the ADP1051 is to control a dual-ended topology
(such as full bridge, half bridge, or push pull), enable the dual-ended
topology mode using Register 0xFE13[6]. Then the modulation
limit in each half cycle is one half of the modulation value pro-
grammed by Register 0xFE3C.
The modulated edges cannot go beyond one switching cycle. To
extend the modulation range for some applications, the 180°
phase shift can be enabled, using Register 0xFE3B[5:0]. When the
180° phase shift is disabled, the rising edge timing and the falling
edge timing are referred to the start of the switching cycle (see tRx
and tFx in Figure 14). When the 180° phase shift is enabled, the
rising edge timing and the falling edge timing are referred to half
of the switching cycle (see tRY and tFY in Figure 14, which are
referred to tS/2). Therefore, when the 180° phase shift is disabled,
the edges are always located between t0 and tS. When the 180° phase
shift is enabled, the edges are located between tS/2 and 3tS/2.
The 180° phase shift function can be used to extend the maximum
duty cycle in a multiphase, interleaved converter. Figure 15 shows
a dual-phase, interleaved buck converter. The OUTC and OUTD
PWM outputs can be programmed as a 180° phase shift with the
OUTA and OUTB PWM outputs.
The phase shedding function can be used for light load efficiency
improvement. See the Light Load Mode and Deep Light Load
Mode section for more information.
The ADP1051 GUI is recommended for evaluating this feature.
DC
INPUT
DRIVER
LOAD
DRIVER
Figure 15. Dual-Phase Interleaved Buck Converter Controlled by the ADP1051
ADAPTIVE DEAD TIME COMPENSATION (ADTC)
The ADTC registers (Register 0xFE5A to Register 0xFE60 and
Register 0xFE66) allow the dead time between the PWM edges to
be adapted on the fly. The ADP1051 uses the ADTC function only
when the CS1 current value (which represents the input current)
falls below the ADTC threshold (programmed in Register 0xFE5A).
The ADP1051 GUI allows the user to easily program the dead time
values, and it is recommended that the GUI be used for this purpose.
Before the ADTC is configured, its threshold must be programmed.
Each individual PWM rising and falling edge (tRx and tFx) can then
be programmed (Register 0xFE5B to Register 0xFE60) to have a
specific dead time offset at a CS1 current of 0 A.
This offset can be positive or negative and is relative to the nominal
edge position. When the CS1 current is between 0 A and the
ADTC threshold, the amount of dead time is linearly adjusted in
steps of 5 ns.
Rev. B | Page 16 of 108
Share Link: 