AT88SC1003-09PT View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT88SC1003-09PT

1K EEPROM–Security Logic with Three Application Zones

Atmel Corporation 

Figure 10. Erase Operation Application Zone 1 (AZ1)

Reset

Read

Compare EZ1

(A)

Address Ax

A0

A1

A2

A431

A432 A433

A478

A479

Erase

(B)

A480

Read

(C)

(D)

A481

RST

CLK

I/O

DX

PGM

D0

D1

Output

CD432

CD433

CD479

Input

Input Output

1

Input

D480

Output

E1 flag

Note:

An = Internal Address, Dn = Read data (output), CDn = Compare data (input).

This diagram illustrates the protocol for setting the E1 flag in Security Level 2 (issuer fuse blown). Erase operations in Security

Level 1 within Application Zone 1 do not require setting of the E1 flag. In Security Level 1, an erase operation on any bit in Appli-

cation Zone 1 will erase the entire zone.

A = Compare sequences of EZ1. If the comparison is valid, the EZ1 flag is set to “1”, enabling erasure of AZ1.

B = If E1 is set to “1”, an erase operation on Bit 480 will erase Bits 176–431 (AZ1).

C = After the falling edge of CLK, the device will drive the I/O contact to the logic state of the existing data in Bit 480. The state

of this bit is not affected by the AZ1 erase operation.

D = After the falling edge of CLK, the address is incremented and the state of the next bit is driven on the I/O contact.

24 AT88SC1003

2035B–SMEM–08/03

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