ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA64L-8MI
Atmel Corporation
ATMEGA64L-8MI Datasheet PDF : 363 Pages
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8-bit Timer/Counter
Register Description
Timer/Counter Control
Register – TCCR0
Bit
Read/Write
Initial Value
7
FOC0
W
0
6
WGM00
R/W
0
5
COM01
R/W
0
4
COM00
R/W
0
3
WGM01
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is
written when operating in PWM mode. When writing a logical one to the FOC0 bit, an
immediate Compare Match is forced on the waveform generation unit. The OC0 output
is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented
as a strobe. Therefore it is the value present in the COM01:0 bits that determines the
effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of oper-
ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table
52 and “Modes of Operation” on page 96.
Table 52. Waveform Generation Mode Bit Description(1)
WGM01 WGM00 Timer/Counter Mode of
Mode (CTC0) (PWM0) Operation
TOP
Update of TOV0 Flag
OCR0 at Set on
0
0
0
Normal
0xFF Immediate MAX
1
0
1
PWM, Phase Correct
0xFF TOP
BOTTOM
2
1
0
CTC
OCR0 Immediate MAX
3
1
1
Fast PWM
0xFF TOP
MAX
Note:
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the
COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC0 pin must be set in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the
WGM01:0 bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0
bits are set to a Normal or CTC mode (non-PWM).
102 ATmega64(L)
2490G–AVR–03/04
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