• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter0 changes counting direction at 0x00.
Timer/Counter Prescaler Figure 45. Prescaler for Timer/Counter0
clkOSC
TOSC1
clkT0S
Clear
10-BIT T/C PRESCALER
AS0
PSR0
0
CS00
CS01
CS02
TIMER/COUNTER0 CLOCK SOURCE
clkT0
The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to
the main system clock clkOSC. By setting the AS0 bit in ASSR, Timer/Counter0 is asyn-
chronously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real
Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from
Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve
as an independent clock source for Timer/Counter0. The Oscillator is optimized for use
with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not
recommended.
For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64,
clkT0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be
selected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to
operate with a predictable prescaler.
108 ATmega64(L)
2490G–AVR–03/04