ATmega64(L)
Figure 145. Parallel Programming Timing, Loading Sequence with Timing
Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t XLXH
t XLPH
t PLXH
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 144 (i.e. tDVXH, tXHXL, and tXLDX) also apply
to loading operation.
Figure 146. Parallel Programming Timing, Reading Sequence (Within the Same Page)
with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
t XLOL
t BHDV
BS1
OE
t OLDV
t OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 144 (i.e. tDVXH, tXHXL, and tXLDX) also apply
to reading operation.
2490G–AVR–03/04
305