ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA64L-8MI
Atmel Corporation
ATMEGA64L-8MI Datasheet PDF : 363 Pages
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Serial Downloading
Table 127. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol Parameter
Min Typ Max Units
VPP
IPP
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
tXLPH
tPLXH
tBVPH
tPHPL
tPLBX
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
tBVDV
tOLDV
tOHDZ
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High(1)
WR Low to RDY/BSY High for Chip Erase(2)
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
11.5
67
200
150
67
0
0
150
67
150
67
67
67
67
150
0
3.7
7.5
0
0
12.5
V
250 µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
µs
4.5 ms
9
ms
ns
250 ns
250 ns
250 ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock
bits commands.
2. tWLRH_CE is valid for the Chip Erase command.
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 128 on page 307, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface. Note that throughout the descrip-
tion about Serial downloading, MOSI and MISO are used to describe the serial data in
and serial data out, respectively. For ATmega64, these pins are mapped to PDI and
PDO.
306 ATmega64(L)
2490G–AVR–03/04
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