Watchdog Reset
ATmega64(L)
When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
tTOUT. Refer to page 54 for details on operation of the Watchdog Timer.
Figure 27. Watchdog Reset During Operation
CC
CK
MCU Control and Status
Register – MCUCSR(1)
The MCU Control and Status Register provides information on which reset source
caused an MCU Reset.
Bit
7
6
JTD
–
Read/Write
R/W
R
Initial Value
0
0
5
4
3
2
1
0
–
JTRF WDRF BORF EXTRF PORF MCUCSR
R
R/W
R/W
R/W
R/W
R/W
0
See Bit Description
Note: 1. Only EXTRF and PORF are available in mega103 compatibility mode.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Brown-out Reset,
or by writing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
53
2490G–AVR–03/04