ATMEGA64-16MI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA64-16MI
Atmel Corporation
ATMEGA64-16MI Datasheet PDF : 363 Pages
| |||
ATmega64(L)
Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and
WDTON
M103C
WDTON
WDT
Safety Initial
Level State
How to
Disable the
WDT
How to
Change
Time-out
Unprogrammed Unprogrammed
1
Disabled Timed
sequence
Timed
sequence
Unprogrammed Programmed
2 Enabled Always
enabled
Timed
sequence
Programmed
Unprogrammed
0
Disabled Timed
sequence
No restriction
Programmed Programmed
2 Enabled Always
enabled
Timed
sequence
Figure 28. Watchdog Timer
WATCHDOG
OSCILLATOR
Watchdog Timer Control
Register – WDTCR
Bit
7
6
5
4
3
2
1
0
–
–
–
WDCE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 58.
55
2490G–AVR–03/04
Share Link: 