C8051F002 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

20.1.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and

load it into the corresponding module’s 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn

and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-

high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative

edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt

request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the

CPU vectors to the interrupt service routine, and must be cleared by software.

Figure 20.3. PCA Capture Mode Diagram

PCA Interrupt

PCA0CPMn

ECCMT P E

CA A AOWC

OPP TGMC

MPN n n n F

nnn

n

0

000

PCA0CN

CC CCCCC

FR CCCCC

FFFFF

43210

Port I/O

Crossbar CEXn

0

1

0

1

PCA0CPLn PCA0CPHn

Capture

PCA

Timebase

PCA0L

PCA0H

Rev. 1.7

156

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