C8051F002 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

20.1.2. Software Timer (Compare) Mode

In Software Timer mode, the PCA counter/timer is compared to the module’s 16-bit capture/compare register

(PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to

logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically

cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.

Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode.

Figure 20.4. PCA Software Timer Mode Diagram

Write to

PCA0CPLn

0

ENB

Reset

Write to

PCA0CPHn ENB

1

PCA0CPMn

ECCMT P E

CA A AOWC

OP P TGMC

MPN n n n F

nnn

n

00 00x

Enable

PCA0CPLn PCA0CPHn

PCA Interrupt

PCA0CN

CC CCCCC

FR CCCCC

FFFFF

43210

16-bit Comparator

Match

0

1

PCA

Timebase

PCA0L

PCA0H

20.1.3. High Speed Output Mode

In this mode, each time a match occurs between the PCA Timer Counter and a module’s 16-bit capture/compare

register (PCA0CPHn and PCA0CPLn) the logic level on the module’s associated CEXn pin will toggle. Setting the

TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-Speed Output mode.

Figure 20.5. PCA High Speed Output Mode Diagram

Write to

PCA0CPLn

0

ENB

Reset

Write to

PCA0CPHn ENB

1

PCA0CPMn

ECCMT P E

CA A AOWC

OP P TGMC

MPN n n n F

nnn

n

00

0x

PCA Interrupt

PCA0CPLn PCA0CPHn

PCA0CN

CC CCCCC

FR CCCCC

FFFFF

43210

Enable

16-bit Comparator

PCA

Timebase

PCA0L

PCA0H

Match

Toggle

0

1

TOGn

0 CEXn Crossbar

1

Port I/O

157

Rev. 1.7

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