C8051F066 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F066 Datasheet PDF : 328 Pages
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C8051F060/1/2/3/4/5/6/7
Figure 6.6. DMA0IPT: DMA0 Instruction Write Address Register
SFR Page: 3
SFR Address: 0xDD
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7-6: Unused.
Bits 5-0: DMA0 instruction address to write (or read). When DMA0IDT is written or read, this register
will be incremented to point to the next instruction address.
Figure 6.7. DMA0IDT: DMA0 Instruction Write Data Register
SFR Page: 3
SFR Address: 0xDE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value†
CCNV DIFFSEL ADC1EN ADC0EN
-
-
-
-
xxxxxxxx
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit 7: CCNV: Continuous Conversion.
0: Disable Continuous Conversion.
1: Enable Continuous Conversion. Repeat Counter value is ignored, and conversions will
continue.
Bit 6: DIFFSEL: Wait for data in differential mode.
0: Differential Data will not be collected.
1: Wait for differential data, and store to XRAM.
Bit 5: ADC1EN: Wait for data from ADC1.
0: ADC1 Data will not be collected.
1: Wait for ADC1 data, and store to XRAM.
Bit 4: ADC0EN: Wait for data from ADC0.
0: ADC0 Data will not be collected.
1: Wait for ADC0 data, and store to XRAM. If DIFFSEL is also ‘1’, only the differential data
will be stored.
Bits 3-0: RESERVED. Write to 0000b.
For more details on DMA instruction words, see Section “6.2. DMA0 Instruction Format” on page 76.
† This register points to a dedicated RAM location and its reset value is indeterminate.
82
Rev. 1.2
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