C8051F066 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F066

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

7.2.2. Tracking Modes

The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2

input is continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1,

ADC2 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-

ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR2 signal is used to ini-

tiate conversions in low-power tracking mode, ADC2 tracks only when CNVSTR2 is low; conversion

begins on the rising edge of CNVSTR2 (see Figure 7.3). Tracking can also be disabled (shutdown) when

the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when

AMUX settings are frequently changed, due to the settling time requirements described in Section

“7.2.3. Settling Time Requirements” on page 91.

Figure 7.3. 10-Bit ADC Track and Conversion Example Timing

CNVSTR2

(AD2CM[1:0]=10)

SAR Clocks

A. ADC2 Timing for External Trigger Source

1 2 3 4 5 6 7 8 9 10 11

AD2TM=1

Low Power

or Convert

Track

Convert

Low Power

Mode

AD2TM=0

Track or Convert

Convert

Track

Write '1' to AD2BUSY,

Timer 3, Timer 2 Overflow

(AD2CM[1:0]=00, 01, 11)

B. ADC2 Timing for Internal Trigger Source

SAR Clocks

AD2TM=1

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Low Power

or Convert

Track

Convert

Low Power Mode

SAR Clocks

AD2TM=0

1 2 3 4 5 6 7 8 9 10 11

Track or

Convert

Convert

Track

90

Rev. 1.2

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