C8051F066 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F066

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

Figure 7.2. Temperature Sensor Transfer Function

Slope (V / deg C)

Offset (V at 0 Celsius)

VTEMP= (Slope x TempC) + Offset

TempC = (VTEMP- Offset) / Slope

-50

0

50

100

Temperature (Celsius)

7.2. Modes of Operation

ADC2 has a maximum conversion speed of 200 ksps. The ADC2 conversion clock is a divided version of

the system clock, determined by the AD2SC bits in the ADC2CF register (system clock divided by (AD2SC

+ 1) for 0 ≤ AD2SC ≤ 31). The ADC2 conversion clock should be no more than 3 MHz.

7.2.1. Starting a Conversion

A conversion can be initiated in one of four ways, depending on the programmed states of the ADC2 Start

of Conversion Mode bits (AD2CM1-0) in register ADC2CN. Conversions may be initiated by one of the fol-

lowing:

1. Writing a ‘1’ to the AD2BUSY bit of register ADC2CN

2. A Timer 3 overflow (i.e. timed continuous conversions)

3. A rising edge on the CNVSTR2 input signal (Assigned by the crossbar)

4. A Timer 2 overflow

When CNVSTR2 is used as a conversion start source, it must be enabled in the crossbar, and the corre-

sponding pin must be set to open-drain, high-impedance mode (see Section “18. Port Input/Output” on

page 203 for more details on Port I/O configuration).

Writing a ‘1’ to AD2BUSY provides software control of ADC2 whereby conversions are performed "on-

demand". During conversion, the AD2BUSY bit is set to logic 1 and reset to logic 0 when the conversion is

complete. The falling edge of AD2BUSY triggers an interrupt (when enabled) and sets the ADC2 interrupt

flag (AD2INT). Note: When polling for ADC conversion completions, the ADC2 interrupt flag (AD2INT)

should be used. Converted data is available in the ADC2 data registers, ADC2H and ADC2L, when bit

AD2INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, low

byte overflows are used if the timer is in 8-bit mode; and high byte overflows are used if the timer is in 16-

bit mode. See Section “24. Timers” on page 287 for timer configuration.

Rev. 1.2

89

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