ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
ISPGDX160V-3Q208I Datasheet PDF : 36 Pages
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Specifications ispGDX160V/VA
Description (Continued)
found in each I/O cell. Each output has individual, pro- In addition, there are no pin-to-pin routing constraints for
grammable I/O tri-state control (OE), output latch clock 1:1 or 1:n signal routing. That is, any I/O pin configured
(CLK), clock enable (CLKEN), and two multiplexer con- as an input can drive one or more I/O pins configured as
trol (MUX0 and MUX1) inputs. Polarity for these signals
is programmable for each I/O cell. The MUX0 and MUX1
inputs control a fast 4:1 MUX, allowing dynamic selection
of up to four signal sources for a given output. A wider
S 16:1 MUX can be implemented with the MUX expander
feature of each I/O and a propagation delay increase of
2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs
E can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clock-
to-output delays. CLK and CLKEN share the same set of
IC I/O pins. CLKEN disables the register clock when
D CLKEN = 0.
outputs.
The device pins also have the ability to set outputs to
fixed HIGH or LOW logic levels (Jumper or DIP Switch
mode). Device outputs are specified for 24mA sink and
12mA source current (at JEDEC LVTTL levels) and can
be tied together in parallel for greater drive. On the
ispGDXVA, each I/O pin is individually programmable for
3.3V or 2.5V output levels as described later. Program-
mable output slew rate control can be defined
independently for each I/O pin to reduce overall ground
bounce and switching noise.
Through in-system programming, connections between
V E I/O pins and architectural features (latched or registered
inputs or outputs, output enable control, etc.) can be
defined. In keeping with its data path application focus,
E U the ispGDXV devices contain no programmable logic
arrays. All input pins include Schmitt trigger buffers for
noise immunity. These connections are programmed
D IN into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration
is saved even when the power is removed from the
device.
All I/O pins are equipped with IEEE1149.1-compliant
Boundary Scan Test circuitry for enhanced testability. In
addition, in-system programming is supported through
the Test Access Port via a special set of private com-
mands.
The ispGDXV I/Os are designed to withstand “live inser-
tion” system environments. The I/O buffers are disabled
during power-up and power-down cycles. When design-
ing for “live insertion,” absolute maximum rating conditions
for the Vcc and I/O pins must still be met.
T T Table 1. ispGDXV Family Members
EC N I/OPins
O I/O-OE Inputs*
LI/O-CLK / CLKEN Inputs*
I/O-MUXsel1 Inputs*
E C I/O-MUXsel2 Inputs*
Dedicated Clock Pins**
S IS EPEN
TOE
BSCAN Interface
DRESET
ispGDXVA Device
ispGDX80VA ispGDX160VA ispGDX240VA
80
160
240
20
40
60
20
40
60
20
40
60
20
40
60
2
4
4
1
1
1
1
1
1
4
4
4
1
1
1
Pin Count/Package
100-Pin TQFP
208-Pin PQFP 388-Ball fpBGA
208-Ball fpBGA
272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to
25% of the I/Os.
** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and
CLKEN3 respectively in all devices.
2
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