ISPGDX160V-3Q208I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

ISPGDX160V-3Q208I

In-System Programmable 3.3V Generic Digital Crosspoint

Lattice Semiconductor

ISPGDX160V-3Q208I Datasheet PDF : 36 Pages

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Specifications ispGDX160V/VA

I/O MUX Operation

allow adjacent I/O cell outputs to be directly connected

without passing through the global routing pool. The

MUX1 MUX0

Data Input Selected

relationship between the [N+i] adjacent cells and A, B, C

and D inputs will vary depending on where the I/O cell is

located on the physical die. The I/O cells can be grouped

into “normal” and “reflected” I/O cells or I/O “hemi-

spheres.” These are defined as:

S Flexible mapping of MUXselx to MUXx allows the user to

change the MUX select assignment after the ispGDXV/

VA device has been soldered to the board. Figure 1

E shows that the I/O cell can accept (by programming the

appropriate fuses) inputs from the MUX outputs of four

adjacent I/O cells, two above and two below. This en-

IC ables cascading of the MUXes to enable wider (up to

16:1) MUX implementations.

Device

Normal I/O Cells

ispGDX80VA

TBA

ispGDX160V/VA B19-B0, A39-A20,

A19-A0, D39-D20

ispGDX240VA

TBA

Reflected I/O Cells

TBA

B20-B39, C0-C19,

C20-C39, D0-D19

TBA

D The I/O cell also includes a programmable flow-through

V latch or register that can be placed in the input or output

E path and bypassed for combinatorial outputs. As shown

in Figure 1, when the input control MUX of the register/

E latch selects the “A” path, the register/latch gets its inputs

U from the 4:1 MUX and drives the I/O output. When

selecting the “B” path, the register/latch is directly driven

D by the I/O input while its output feeds the GRP. The

IN programmable polarity Clock to the latch or register can

be connected to any I/O in the I/O-CLK/CLKEN set (one-

quarter of total I/Os) or to one of the dedicated clock input

T pins (Yx). The programmable polarity Clock Enable input

T to the register can be programmed to connect to any of

the I/O-CLK/CLKEN input pin set or to the global clock

C enable inputs (CLKENx). Use of the dedicated clock

N inputs gives minimum clock-to-output delays and mini-

mizes delay variation with fanout. Combinatorial output

E mode may be implemented by a dedicated architecture

O bit and bypass MUX. I/O cell output polarity can be

programmed as active high or active low.

Table 2 shows the relationship between adjacent I/O

cells as well as their relationship to direct MUX inputs.

Note that the MUX expansion is circular and that I/O cell

B20, for example, draws on I/Os B19 and B18, as well as

B21 and B22, even though they are in different hemi-

spheres of the physical die. Table 2 shows some typical

cases and all boundary cases. All other cells can be

extrapolated from the pattern shown in the table.

Figure 2. I/O Hemisphere Configuration of

ispGDX160V/VA

I/O cell 0 I/O cell 159

D39

D20 D19

EL C MUX Expander Using Adjacent I/O Cells

The ispGDXV/VA allows adjacent I/O cell MUXes to be

S IS cascaded to form wider input MUXes (up to 16 x 1)

without incurring an additional full Tpd penalty. However,

there are certain dependencies on the locality of the

adjacent MUXes when used along with direct MUX

D inputs.

B19 B20

B39

I/O cell 79 I/O cell 80

Adjacent I/O Cells

Direct and Expander Input Routing

Expansion inputs MUXOUT[n-2], MUXOUT[n-1],

MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable

for each I/O cell MUX. These expansion inputs share the

same path as the standard A, B, C and D MUX inputs, and

Table 2 also illustrates the routing of MUX direct inputs

that are accessible when using adjacent I/O cells as

inputs. Take I/O cell D23 as an example, which is also

shown in Figure 3.

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