M50FLW040AN5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

Status Register

M50FLW040A, M50FLW040B

5.3.4

5.3.5

Block Protection status (Bit SR1)

The Block Protection Status bit can be used to identify if the Program or Erase operation has

tried to modify the contents of a protected block. When the Block Protection Status bit is to

‘0’, no Program or Erase operations have been attempted to protected blocks since the last

Clear Status Register command or hardware reset. When the Block Protection Status bit is

‘1’, a Program or Erase operation has been attempted on a protected block.

Once it is set to ‘1’, the Block Protection Status bit can only be reset to ‘0’ by a Clear Status

Register command or by a hardware reset. If it is set to ‘1’, it should be reset before a new

Program or Erase command is issued, otherwise the new command will appear to have

failed, too.

Using the A/A Mux Interface, the Block Protection Status bit is always ‘0’.

Reserved (Bit SR0)

Bit 0 of the Status Register is reserved. Its value should be masked.

Table 14. Status Register bits

Operation

SR7 SR6 SR5 SR4 SR3 SR2 SR1

Program active

‘0’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program suspended

‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’

Program completed successfully

‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program failure due to VPP Error

‘1’ X(1) ‘0’ ‘1’ ‘1’ ‘0’ ‘0’

Program failure due to Block Protection (FWH/LPC

Interface only)

‘1’

X(1)

‘0’

‘1’

‘0’

‘0’

‘1’

Program failure due to cell failure

‘1’ X(1)) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase active

‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase suspended

‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase completed successfully

‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase failure due to VPP Error

Erase failure due to Block Protection (FWH/LPC

Interface only)

‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’

‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’

Erase failure due to failed cell(s) in block

‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’

1. For Program operations during Erase Suspend Bit SR6 is ‘1’, otherwise Bit SR6 is ‘0’.

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