M50FLW040AN5TP View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M50FLW040AN5TP

4-Mbit (5 × 64 Kbyte blocks + 3 × 16 × 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory

STMicroelectronics 

M50FLW040A, M50FLW040BFirmware hub/low pin count (FWH/LPC) interface Configuration Reg-

6

Firmware hub/low pin count (FWH/LPC) interface

Configuration Registers

When the Firmware Hub Interface/Low Pin Count is selected, several additional registers

can be accessed. These registers control the protection status of the Blocks, read the

General Purpose Input pins and identify the memory using the manufacturer code. See

Table 15 for the memory map of the Configuration Registers. The Configuration registers

are accessed directly without using any specific command code. A single Bus Write or Bus

Read Operation, with the appropriate address (including A22=0), is all that is needed.

6.1

6.1.1

6.1.2

Lock Registers

The Lock Registers control the protection status of the Blocks. Each Block has its own Lock

Register. Three bits within each Lock Register control the protection of each block: the Write

Lock Bit, the Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written. Care should be taken, though, when writing.

Once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be

made until it is cleared again by a reset or power-up.

See Table 16 for details on the bit definitions of the Lock Registers.

Write Lock

The Write Lock Bit determines whether the contents of the Block can be modified (using the

Program or Erase Command). When the Write Lock Bit is set, ‘1’, the block is write

protected – any operations that attempt to change the data in the block will fail, and the

Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the block is not

write protected by the Lock Register, and may be modified, unless it is write protected by

some other means.

If the Top Block Lock signal, TBL, is Low, VIL, then the Top Block (Block 7) is write protected,

and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, VIL, then the Main

Blocks (Blocks 0 to 6) are write protected, and cannot be modified.

After power-up, or reset, the Write Lock Bit is always set to ‘1’ (write-protected).

Read Lock

The Read Lock bit determines whether the contents of the Block can be read (in Read

mode). When the Read Lock Bit is set, ‘1’, the block is read protected – any operation that

attempts to read the contents of the block will read 00h instead. When the Read Lock Bit is

reset, ‘0’, read operations are allowed in the Block, and return the value of the data that had

been programmed in the block.

After power-up, or reset, the Read Lock Bit is always reset to ‘0’ (not read-protected).

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