MT90866
Data Sheet
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LTM LTM LTM LSAB LSAB LSAB LSAB LSAB LCAB LCAB LCAB LCAB LCAB LCAB LCAB LCAB
2
1
0
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit
15 -13
Name
Description
LTM2 - 0 Throughput Delay and Message Channel Control Bits: These three bits control the
local ST-BUS output.
LTM2-0
000
001
010
011
100
101
110
111
Throughput delay and Message Mode control
Per-channel variable delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel and stream.
The local ST-BUS output is from the local ST-BUS input.
Per-channel constant delay from local interface; the content of the connection
memory is the local data memory address of the switched input channel and stream.
The local ST-BUS output is from the local ST-BUS input.
Per-channel variable delay from backplane interface; the content of the connection
memory is the backplane data memory address of the switched input channel and
stream. The local ST-BUS output is from the backplane CT-Bus input.
Per-channel constant delay from the backplane interface; the content of the
connection memory is the backplane data memory address of the switched input
channel and stream. The local ST-BUS output is from backplane CT-Bus input.
Per-channel message mode; only the lower byte (bits 7 to 0) of the connection
memory location will be presented to the local ST-BUS output channel.
Per-channel BER pattern; the pseudo random BER test pattern will be presented to
the local ST-BUS output channel.
Per-channel high-impedance. The local ST-BUS output is high-impedance.
Reserved
000
001
010
011
100
101
110
111
Input Source
Local
Backplane
x
x
x
x
Var.
delay
x
x
Const.
delay
Msg
Mode
x
x
x
Reserved
BER
.
Output HiZ
x
x
12 - 8
LSAB4 -
LSAB0
Source Stream Address Bits: These five bits refer to the number of the data streams for
the source (local or backplane) connection.
Table 29 - Local Connection Memory Low Bits
65
Zarlink Semiconductor Inc.