MT90866
Data Sheet
Local Input Bit Delay
LIDn4
Corresponding Delay Bits
LIDn3
LIDn2
LIDn1
+ 1/2 data rate clock period
0
0
0
1
+ 3/4 data rate clock period
0
0
0
1
+ 1 data rate clock period
0
0
1
0
+ 1 1/4 data rate clock period
0
0
1
0
+ 1 1/2 data rate clock period
+ 1 3/4 data rate clock period
0
0
1
1
0
0
1
1
+ 2 data rate clock period
0
1
0
0
..........
...........
+ 7 3/4 data rate clock period
1
1
1
1
Table 13 - Local Input Bit Delay Programming (continued)
LIDn0
0
1
0
1
0
1
0
1
ST_FPo0/1
input data
input data
input data
input data
input data
input data
bit7
bit7
bit7
bit7
bit7
bit7
Bit Delay 0
LID=00000
Bit Delay 1/4
LID=00001
Bit Delay 1/2
LID=00010
Bit Delay 3/4
LID=00011
Bit Delay 1
LID=00100
Bit Delay 1 1/2
LID=00101
Figure 19 - Local Input Bit Delay Timing
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Zarlink Semiconductor Inc.