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MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name
Description
Manufacturer
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Read/Write Address: 002CH for DOM2 Register
Reset Value: 0000H
15 14 13 12
11
10
9
0 0 0 0 HRST MRST FDM1
8
FDM0
7
BFEN
6
AFEN
5
CNIN
4
DIV1
3
DIV0
2
CNS2
1
CNS1
0
CNS0
Bit
15 - 12
11
10
9-8
Name
Unused
HRST
MRST
FDM1 -
FDM0
Description
Reserved.
DPLL Hold Memory Reset Bit: When HRST is low, the DPLL hold memory
circuit is in functional mode. When HRST is high, the hold memory circuit will be
reset. While the DPLL is in Holdover Mode, pulsing HRST high (or holding it high
continuously) will force the DPLL to the Freerun Mode.
MTIE Reset Bit: When MRST is low, the DPLL MTIE circuit is in functional mode.
When MRST is high, the MTIE circuit will be reset - the DPLL outputs will align
with the nearest edge of the selected reference. When the MT90866 is operating
in the slave mode, this bit MUST be set high to reset the MTIE circuit.
Failure Detect Mode Bits: These two bits control how to choose the Failure
Detection.
FDM1 FDM0
Failure Detection Mode
0
0 Autodetect - Automatic Failure Detection by internal refer-
ence monitor circuit
0
1 External - Failure Detection controlled by external inputs
(PRI_LOS and SEC_LOS)
1
0 Forced Primary - The DPLL is forced to use primary refer-
ence
1
1 Forced Secondary - The DPLL is forced to use secondary
reference
7
BFEN
B Clocks Fail Output Enable Bit: When BFEN is low, FAIL_B output is disabled,
i.e., tri-stated. When BFEN is high, FAIL_B output is enabled.
6
AFEN
A Clocks Fail Output Enable Bit: When AFEN is low, FAIL_A output is disabled,
i.e., tri-stated. When AFEN is high, FAIL_A output is enabled.
5
CNIN
CTREF1 andCTREF2 Inputs Inverted: When CNIN is high, the CTREF1 and
CTREF2 inputs will be inverted, prior to entering the DPLL module. When CNIN is
low, the CTREF1 and CTREF2 inputs will not be inverted.
Table 21 - DPLL Operation Mode (DOM2) Register Bits
58
Zarlink Semiconductor Inc.

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