MT90866
Data Sheet
Bit Name
Description
9 - 8 FP1 - FP0 PRI_REF Frequency Selection Bits: These bits are used to select different clock
frequencies for the primary reference.
FS1
FS0
Primary Reference
0
0
8 kHz
0
1
1.544 MHz
1
0
2.048 MHz
1
1
8.192 MHz (“A Clocks” or “B
Clocks”)
7 - 4 SS3 - SS0 Secondary Clock Reference Input Selection Bits: These bits are used to select secondary
reference input.
SS3 - SS0 Secondary Clock Reference Input
0000
CTREF1
0001
CTREF2
0010
“A Clocks”
0011
“B Clocks”
0100
Reserved
0101
Reserved
0110
Reserved
0111
Reserved
1000
LREF0
1001
LREF1
1010
LREF2
1011
LREF3
1100
LREF4
1101
LREF5
1110
LREF6
1111
LREF7
Table 20 - DPLL Operation Mode (DOM1) Register Bits (continued)
56
Zarlink Semiconductor Inc.