MT90866
Data Sheet
Bit
Name
Description
4 -3
DIV1 - DIV0 Divider Bits: These two bits define the relationship between the input reference
and the NREFo output.
DIV1
0
0
1
1
DIV0
NREFo Output
0 Input reference
1 Input reference/193 (8 KHz signal when input
reference clock = 1.544 MHz)
0 Input reference/256 (8 KHz signal when input
reference clock = 2.048 MHz)
1 Reserved
2-0
CNS2 - CNS0 NREFo Source Selection Bits: These three bits select one of the LREF7 -
LREF0 to be the NREFo source.
CNS2
0
0
0
0
1
1
1
1
CNS1
0
0
1
1
0
0
1
1
CNS0
0
1
0
1
0
1
0
1
NREFo Source
LREF0
LREF1
LREF2
LREF3
LREF4
LREF5
LREF6
LREF7
Table 21 - DPLL Operation Mode (DOM2) Register Bits (continued)
59
Zarlink Semiconductor Inc.