MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc
Part Name
Description
Manufacturer
MT90866
Zarlink Semiconductor Inc
MT90866 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
Read/Write Addresses:
Reset value:
001CH for BOAR0 register,
001EH for BOAR2 register,
0000H for all BOAR registers.
001DH for BOAR1 register,
001FH for BOAR3 register,
BOAR0
15
BOA
71
14
BOA
70
13
BOA
61
12
BOA
60
11
BOA
51
10
BOA
50
9
BOA
41
8
BOA
40
7
BOA
31
6
BOA
30
5
BOA
21
4
BOA
20
3
BOA
11
2
BOA
10
1
BOA
01
0
BOA
00
BOAR1 BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA
151 150 141 140 131 130 121 120 111 110 101 100 91
90
81
80
BOAR2 BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA
231 230 221 220 211 210 201 200 191 190 181 180 171 170 161 160
BOAR3 BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA BOA
311 310 301 300 291 290 281 280 271 270 271 260 251 250 241 240
Name)
BOAn1, BOAn0
(See Note 1)
Description
Backplane Output Advancement Bits 1 - 0: These two bits represent the amount of
offset that a particular stream output can be advanced. When the offset is zero, the
serial output stream has normal alignment with the frame pulse.
BOAn1 BOAn0
0
0
0
1
1
0
1
1
Output
Advancement
0 ns
7.5 ns
15 ns
22.5 ns
C8_A_io
or C8_B_io
period
0
- 1/16
- 1/8
- 3/16
8.192 Mb/s
(bit)
0
- 1/16
- 1/8
- 3/16
16.384 Mb/s
(bit)
0
- 1/8
- 1/4
- 3/8
Note 1: n denotes a STio stream number from 0 to 31.
Table 14 - Backplane Output Advancement Registers (BOAR0 to BOAR3) Bit
FRAME_A_io
or FRAME_B_io
C64
(internal clock)
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
8 Mb/s Stream
Bit 7
advancement is 0ns
BOA=00
Bit 7
advancement is 7.5 ns
BOA=01
Bit 7
advancement is 15 ns
BOA=10
Bit 7
denotes the starting point of the bit cell
advancement is 22.5 ns
BOA=11
Figure 20 - Example of Backplane Output Advancement Timing
52
Zarlink Semiconductor Inc.
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