MT90866 View Datasheet(PDF) - Zarlink Semiconductor Inc

Part Name

Description

Manufacturer

MT90866

Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch

Zarlink Semiconductor Inc 

MT90866

Data Sheet

Read/Write Addresses:

Reset value:

0020H for LOAR0 register,

0022H for LOAR2 register,

0000H for all LOAR registers.

0021H for LOAR1 register,

0023H for LOAR3 register,

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOAR0 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA

71 70 61 60 51 50 41 40 31 30 21 20 11 10 01 00

LOAR1 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA

151 150 141 140 131 130 121 120 111 110 101 100 91 90 81 80

LOAR2 LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA LOA

231 230 221 220 211 210 201 200 191 190 181 180 171 170 161 160

LOAR3 0 0 0 0 0 0 0 0 LOA LOA LOA LOA LOA LOA LOA LOA

271 270 271 260 251 250 241 240

Name

LOAn1,

LOAn0

(See Note 1)

Description

Local Output Advancement Bits 1-0: These two bits represent the amount of offset

that a particular stream output can be advanced. When the offset is zero, the serial

output stream has normal alignment with the frame pulse.

LOAn1

0

0

1

1

LOAn0

0

1

0

1

Output

Advancement

0 ns

- 7.5 ns

- 15 ns

- 22.5 ns

C8_A_io

or C8_B_io

period

0

- 1/16

- 1/8

- 3/16

2.048Mb/s

(bit)

0

- 1/64

- 1/32

- 3/64

4.096Mb/s

(bit)

0

- 1/32

- 1/16

- 3/32

8.192Mb/s

(bit)

0

- 1/16

- 1/8

- 3/16

Note 1: n denotes a STi stream number from 0 to 27.

Table 15 - Local Output Advancement Registers (LOAR0 to LOAR3) Bits

ST_FPo0/1

C64

(internal clock)

8 Mb/s Stream

8 Mb/s Stream

8 Mb/s Stream

8 Mb/s Stream

Bit 7

Bit 7

Bit 7

Bit 7

denotes the starting point of the bit cell

Figure 21 - Local Output Advancement Timing

advancement is 0 ns

LOA=00

advancement is 7.5 ns

LOA=01

advancement is 15 ns

LOA=10

advancement is 22.5 ns

LOA=11

53

Zarlink Semiconductor Inc.

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