MT90866
Data Sheet
AC Electrical Characteristics† - Output Frame Pulse and Output Clock Timing
Characteristic
Sym.
Min. Typ.‡ Max. Units Notes
1 Internal Timing Variation
∆∗
6.50
7.50
ns
2 Backplane Frame Boundary Offset
tFBOS 1.25-∆
2.5+∆
ns
3 FRAME_A_io, FRAME_B_io Output Pulse tCFPOW 122-∆ 122 122+∆
ns
Width
CL=30pF
4 Delay from FRAME_A_io, FRAME_B_io
output falling edge to C8_a_io,C8_B_io
tCFODF 61-∆/2
61+∆/2 ns
output rising edge
5 Delay from C8_A_io,C8_B_io output rising
edge to FRAME_A_io,FRAME_B_io output
rising edge
tCFODR 61-∆/2
61+∆/2 ns
6 C8_A_io, C8_B_io Output Clock Period
7 C8_A_io, C8_B_io Output High Time
8 C8_A_io, C8_B_io Output Low Time
9 C8_A_io, C8_B_io Output Rise Time
10 C8_A_io, C8_B_io Output Fall Time
11 C32/64o (32.768 MHz) Output Delay Time
12 C32/64o (32.768 MHz) Period
13 C32/64o (32.768 MHz) High Time
14 C32/64o (32.768 MHz) Low Time
15 C32/64o (65.536 MHz) Period
16 C32/64o (65.536 MHz) High Time
17 C32/64o (65.536 MHz) Low Time
18 C32/64o Clock Rise Time
(32.768 MHz or 65.536 MHz)
tC8MP 122-∆ 122 122+∆
ns
tC8MH 61-∆/2
61+∆/2 ns
tC8ML 61-∆/2
61+∆/2 ns
trC8o
13
ns
tfC8o
14
tC32MOD
∆
ns
tC32MP 30.5-∆ 30.5 30.5+∆
ns
tC32MH 15.25-∆/2
15.25+∆/2 ns
tC32ML 15.25-∆/2
15.25+∆/2 ns
tC64MP 15.25-∆/2 15.25 15.25+∆/2 ns
tC64MH
∆
0.5+∆
ns
tC64ML
∆
5.5+∆
ns
tr32o
5
ns
CL=30pF
CL=30pF
19 C32/64o Clock Fall Time
tf32o
(32.768 MHz or 65.536 MHz)
6
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* The AC electrical characteristics are listed as a function of the internal timing variation (∆) to highlight the value of each parameter independent
of the variation. It is important to choose the maximum or minimum ∆ value correctly for worst case timing calculation. When adding parameters
for timing calculation, it is sufficient to include this ∆ only once in the calculation.
69
Zarlink Semiconductor Inc.