ST7SCR
I/O PORTS (Cont’d)
9.3 I/O Port Implementation
The hardware implementation on each I/O port de-
pends on the settings in the DDR register and spe-
cific feature of the I/O port such as true open drain.
9.3.1 Port A
Table 9. Port A Description
PORT A
PA[5:0]
PA6
*Reset State
Input
without pull-up *
without pull-up
I/O
Output
push-pull or open drain with software selectable pull-up
-
Figure 21. PA0, PA1, PA2, PA3, PA4, PA5 Configuration
ALTERNATE 1
OUTPUT
0
ALTERNATE ENABLE
VDD
P-BUFFER
DR
LATCH
DDR
LATCH
DDR SEL
ALTERNATE ENABLE
PULL-UP 1)
VDD
PAD
DR SEL
1
ALTERNATE INPUT
0
N-BUFFER
ALTERNATE ENABLE
VSS
CMOS SCHMITT TRIGGER
DIODES
Note 1: selectable by PAPUCR register
Figure 22. PA6 Configuration
DR SEL
VDD
PAD
CMOS SCHMITT TRIGGER
DIODES
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