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ST7PSCR1E4M1/XXX View Datasheet(PDF) - STMicroelectronics

Part Name
Description
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ST7PSCR1E4M1/XXX Datasheet PDF : 102 Pages
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ST7SCR
MISCELLANEOUS REGISTER 3 (MISCR3)
Reset Value: 0000 0000 (00h)
Read/Write
7
0
CTR CTR CTR CTR
L1_A L0_A L1_C L0_C
-
-
-
-
This register is used to configure the edge and the
level sensitivity of the Port A and Port C external
interrupt. This means that all bits of a port must
have the same sensitivity.
If a write access modifies bits 7:4, it clears the
pending interrupts.
CTRL0_C, CTRL1_C : Sensitivity on port C
CTRL0_A, CTRL1_A : Sensitivity on port A
CTR CTR
L1_X L0_X
00
01
10
11
External
Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
MISCELLANEOUS REGISTER 4 (MISCR4)
Reser Value : 0000 0000 (00h).
Read/Write
7
0
-
PLL CLK_
_ON SEL
-
-
-
- LOCK
Bit 7 = Reserved.
Bit 6 = PLL_ON PLL Activation
0: PLL disabled
1: PLL enabled
Note: The PLL must be disabled before a HALT
instruction.
Bit 5 = CLK_SEL Clock Selection
This bit is set and cleared by software.
0: CPU frequency = 4MHz
1: CPU frequency = 8MHz
Bits 4:1 = Reserved.
Bit 0 = LOCK PLL status bit
0: PLL not locked. fCPU = fOSC external clock fre-
quency.
1: PLL locked. fCPU = 4 or 8 MHz depending on
CLKSEL bit.
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