ST7SCR
10 MISCELLANEOUS REGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Reset Value : 0000 0000 (00h)
Read/Write
7
0
ITM ITM ITM ITM ITM ITM ITM ITM
7
6
5
4
3
2
1
0
Writing the ITIFREC register enables or disables
external interrupt on Port C. Each bit can be
masked independantly. The ITMx bit masks the
external interrupt on PC.x.
Bits[7:0] = ITM [7:0] Interrupt Mask
0: external interrupt disabled
1: external interrupt enabled
MISCELLANEOUS REGISTER 2 (MISCR2)
Reset Value : 0000 0000 (00h)
Read/Write
7
0
CRD ITM ITM ITM ITM ITM ITM
- IRM 14 13 12 11 10
9
Writing the ITIFREA register enables or disables
external interrupt on port A.
Bit 7 = Reserved.
Bit 6 = CRDIRM CRD Insertion/Removal Interrupt
Mask
0: CRDIR interrupt disabled
1: CRDIR interrupt enabled
Bits [5:0] = ITM [14:9] Interrupt Mask
Bit x of MISCR2 masks the external interrupt on
port A.x.
Bit x = ITM n Interrupt Mask n
0: external interrupt disabled on PA.x.
1: external interrupt enabled on PA.x.
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