PCF8578HT View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF8578HT Datasheet PDF : 46 Pages
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NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
master receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices.
In multiple device applications, the hardware subaddress pins of the PCF8579s (A0 to A3)
are connected to VSS or VDD to represent the desired hardware subaddress code. If two or
more devices share the same slave address, then each device must be allocated to a
unique hardware subaddress.
8.9 Display RAM
The PCF8578 contains a 32 × 40-bit static RAM which stores the display data. The RAM
is divided into 4 banks of 40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to and from the RAM via the I2C-bus. The first eight columns of data (0 to 7)
cannot be displayed but are available for general data storage and provide compatibility
with the PCF8579. There is a direct correspondence between X-address and column
output number.
8.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows an individual data byte or a series of data bytes to be written into, or read from, the
display RAM, controlled by commands sent on the I2C-bus.
8.9.2 Subaddress counter
The storage and retrieval of display data is dependent on the content of the subaddress
counter. Storage takes place only when the contents of the subaddress counter match
with the hardware subaddress. The hardware subaddress of the PCF8578, valid in mixed
mode only, is fixed at 0000.
8.10 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus.
The five commands available to the PCF8578 are defined in Table 9.
Table 9. Definition of PCF8578 commands
Command
Operation code
Bit
7
6
5
4
set-mode
C
1
0
T
set-start-bank
C
1
1
1
device-select
C
1
1
0
RAM-access
C
1
1
1
load-X-address C
0
X[5:0]
3
2
E[1:0]
1
1
A[3:0]
G[1:0]
1
0
M[1:0]
B[1:0]
Y[1:0]
Reference
Table 11
Table 12
Table 13
Table 14
Table 15
The most-significant bit of a command is the continuation bit C (see Table 10 and
Figure 16). Commands are transferred in WRITE mode only.
PCF8578_6
Product data sheet
Rev. 06 — 5 May 2009
© NXP B.V. 2009. All rights reserved.
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