PCF8578HT View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF8578HT Datasheet PDF : 46 Pages
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NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
Table 15. Load-X-address - command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6
-
0
fixed value
5 to 0 X[5:0]
0 to 39[1]
RAM column address;
six bits of immediate data, transferred to the
X-address pointer to define one of forty display
RAM columns (see Figure 17)
[1] Values shown in decimal.
8.11 RAM access
1 byte
LSB
0
Y address
Y max
PCF8578_6
Product data sheet
MSB
0
Fig 17. RAM addressing scheme
X address
X max
001aaj920
RAM operations are only possible when the PCF8578 is in mixed mode. In this event its
hardware subaddress is internally fixed at 0000 and the hardware subaddresses of any
PCF8579 used in conjunction with the PCF8578 must start at 0001.
There are three RAM-access modes:
• Character
• Half-graphic
• Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. The
RAM-access command controls the order in which data is written to or read from the RAM
(see Figure 18).
To store RAM data, the user specifies the location into which the first byte will be loaded
(see Figure 19):
• Device subaddress (specified by the device-select command)
• RAM X-address (specified by the bits X[5:0] of the load-X-address command)
• RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes will be written or read according to the chosen RAM-access mode.
Device subaddresses are automatically incremented between devices until the last device
is reached. If the last device has subaddress 15, further display data transfers will lead to
a wrap-around of the subaddress to 0.
Rev. 06 — 5 May 2009
© NXP B.V. 2009. All rights reserved.
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