PCF8578HT View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF8578HT Datasheet PDF : 46 Pages
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NXP Semiconductors
PCF8578
LCD row/column driver for dot matrix graphic displays
10. Static characteristics
Table 17. Static characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Supplies
VDD
VLCD
IDD
supply voltage
LCD supply voltage
supply current
external clock;
fclk = 2 kHz
internal clock;
2.5
-
VDD − 9 -
[1] -
6
-
20
6.0
VDD − 3.5
15
50
VPOR
Logic
power-on reset voltage
Rext(OSC) = 330 kΩ
[2] 0.8
1.3
1.8
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
at pins SYNC and CLK;
VOL = 1 V; VDD = 5 V
at pin SDA;
VSS
-
0.7VDD
-
1
-
3
-
0.3VDD
VDD
-
-
VOL = 0.4 V; VDD = 5 V
IOH
HIGH-level output current
at pins SYNC and CLK;
-
-
−1
VOH = 4 V; VDD = 5 V;
IL
leakage current
at pins SDA, SCL, SYNC,
−1
-
+1
CLK, TEST and SA0;
Vi = VDD or VSS
at pin OSC;
Vi = VDD
−1
-
+1
Ci
capacitance for each I/O pin
[3] -
-
5
LCD outputs
IL
leakage current
Voffset(DC) DC offset voltage
at pins V2 to V5;
−2
Vi = VDD or VLCD
on pins R0 to R7, R8/C8 to
-
R31/C31 and C32 to C39
-
+2
±20
-
RO
output resistance
on row output pins: R0 to [4] -
R7 and R8/C8 to R31/C31
1.5
3
on column output pins:
[4] -
R8/C8 to R31/C31 and C32
to C39
3
6
Unit
V
V
µA
µA
V
V
V
mA
mA
mA
mA
µA
pF
µA
mV
kΩ
kΩ
[1] Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50 % duty factor.
[2] Resets all logic when VDD < VPOR.
[3] Periodically sampled; not 100 % tested.
[4] Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input (V2 to V5, VDD and VLCD)
when the specified current flows through one output under the following conditions (see Table 6 on page 11):
a) Voper = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; Iload = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; Iload = 100 µA.
PCF8578_6
Product data sheet
Rev. 06 — 5 May 2009
© NXP B.V. 2009. All rights reserved.
29 of 46
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