PIC16(L)F1512/3
REGISTER 16-11: AADSTAT: HARDWARE CVD STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
ADCONV
bit 7
R/W-0/0
R/W-0/0
ADSTG<1:0>
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
ADCONV: ADC Conversion Status bit
1 = Indicates ADC in Conversion Sequence for AADRES1H:AADRES1L
0 = Indicates ADC in Conversion Sequence for AADRES0H:AADRES0L (Also reads ‘0’ when
GO/DONE = 0)
ADSTG<1:0>: ADC Stage Status bit
11 = ADC module is in conversion stage
10 = ADC module is in acquisition stage
01 = ADC module is in pre-charge stage
00 = ADC module is not converting (same as GO/DONE = 0)
REGISTER 16-12: AADPRE: HARDWARE CVD PRE-CHARGE CONTROL REGISTER
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
ADPRE<6:0>
bit 7
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-0
Unimplemented: Read as ‘0’
ADPRE<6:0>: Pre-charge Time Select bits(1)
111 1111 = Pre-charge for 127 instruction cycles
111 1110 = Pre-charge for 126 instruction cycles
•
•
•
000 0001 = Pre-charge for 1 instruction cycle (Fosc/4)
000 0000 = ADC pre-charge time is disabled
Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the
pre-charge and acquisition times.
2012-2014 Microchip Technology Inc.
DS40001624C-page 151