PIC16(L)F1512/3
REGISTER 16-18: AADRESxH: HARDWARE CVD RESULT REGISTER MSB ADFM = 1(1)
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
—
—
—
—
—
ADRESx<9:8>
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1-0
Reserved: Do not use.
AD<9:8>: Most Significant ADC results
Note 1: See Section 16.6.11 “Hardware CVD Register Mapping” for more information.
REGISTER 16-19: AADRESxL: HARDWARE CVD RESULT REGISTER LSB ADFM = 1(1)
R/W-x/u
bit 7
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRESx<7:0>
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
AD<7:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result
Note 1: See Section 16.6.11 “Hardware CVD Register Mapping” for more information.
2012-2014 Microchip Technology Inc.
DS40001624C-page 155