PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology
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PIC16F1513T-I/SS Datasheet PDF : 360 Pages
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PIC16(L)F1512/3
REGISTER 16-13: AADACQ: HARDWARE CVD ACQUISITION TIME CONTROL REGISTER
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
ADACQ<6:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-0
Unimplemented: Read as ‘0’
ADACQ<6:0>: Acquisition/Charge Share Time Select bits(1)
111 1111 = Acquisition/charge share for 127 instruction cycles
111 1110 = Acquisition/charge share for 126 instruction cycles
•
•
•
000 0001 = Acquisition/charge share for one instruction cycle (Fosc/4)
000 0000 = ADC Acquisition/charge share time is disabled
Note 1: When the FRC clock is selected as the conversion clock source, it is also the clock used for the
pre-charge and acquisition times.
REGISTER 16-14: AADGRD: HARDWARE CVD GUARD RING CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
GRDBOE(2) GRDAOE(2) GRDPOL(1,2)
—
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other
Resets
bit 7
bit 6
bit 5
bit 4-0
GRDBOE: Guard Ring B Output Enable bit(2)
1 = ADC guard ring output is enabled to ADGRDB pin. Its corresponding TRISx bit must be clear.
0 = No ADC guard ring function to this pin is enabled
GRDAOE: Guard Ring A Output Enable bit(2)
1 = ADC Guard Ring Output is enabled to ADGRDA pin. Its corresponding TRISx, x bit must be clear.
0 = No ADC Guard Ring function is enabled
GRDPOL: Guard Ring Polarity selection bit(1,2)
1 = ADC guard ring outputs start as digital high during pre-charge stage
0 = ADC guard ring outputs start as digital low during pre-charge stage
Unimplemented: Read as ‘0’
Note 1:
2:
When the ADDSEN = 1 and ADIPEN = 1; the polarity of this output is inverted for the second conversion
time. The stored bit value does not change.
Guard Ring outputs are maintained while ADON = 1. The ADGRDA output switches polarity at the start of
the acquisition time.
DS40001624C-page 152
2012-2014 Microchip Technology Inc.
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