PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LC658-I/CL Datasheet PDF : 366 Pages
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PIC18CXX8
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
FSR1H
658
858
---- 0000
---- 0000
---- uuuu
FSR1L
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
BSR
658
858
---- 0000
---- 0000
---- uuuu
INDF2
658
858
N/A
N/A
N/A
POSTINC2
658
858
N/A
N/A
N/A
POSTDEC2
658
858
N/A
N/A
N/A
PREINC2
658
858
N/A
N/A
N/A
PLUSW2
658
858
N/A
N/A
N/A
FSR2H
658
858
---- 0000
---- 0000
---- uuuu
FSR2L
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
658
858
---x xxxx
---u uuuu
---u uuuu
TMR0H
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR0L
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
T0CON
658
858
1111 1111
1111 1111
uuuu uuuu
OSCCON
658
858
---- ---0
---- ---0
---- ---u
LVDCON
658
858
--00 0101
--00 0101
--uu uuuu
WDTCON
RCON(4, 6)
658
858
658
858
---- ---0
00-1 11q0
---- ---0
00-1 qquu
---- ---u
uu-u qquu
TMR1H
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1L
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
658
858
0-00 0000
u-uu uuuu
u-uu uuuu
TMR2
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
PR2
658
858
1111 1111
1111 1111
1111 1111
T2CON
658
858
-000 0000
-000 0000
-uuu uuuu
SSPBUF
658
858
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPADD
658
858
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
658
858
0000 0000
0000 0000
uuuu uuuu
SSPCON1
658
858
0000 0000
0000 0000
uuuu uuuu
SSPCON2
658
858
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware
stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR.
7: Available on PIC18C858 only.
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 35
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