PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

4.6 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

two cycles are required to complete the instruction

(Example 4-2).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW

4.7 Instructions in Program Memory

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = ’0’). Figure 4-1 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ’0’ (See Section 4.4).

The CALL and GOTO instructions have an absolute pro-

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 4-1 shows how the

instruction “GOTO 000006h” is encoded in the program

memory. Program branch instructions that encode a rel-

ative address offset operate in the same manner. The

offset value stored in a branch instruction represents the

number of single word instructions by which the PC will

be offset. Section 23.0 provides further details of the

instruction set.

1. MOVLW 55h

2. MOVWF PORTB

TCY0

Fetch 1

TCY1

Execute 1

Fetch 2

3. BRA SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

TCY2

Execute 2

Fetch 3

TCY3

TCY4

TCY5

Execute 3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TABLE 4-1: INSTRUCTIONS IN PROGRAM MEMORY

Instruction

Opcode

—

MOVLW 055h

0E55h

GOTO 000006h

EF03h, F000h

MOVFF 123h, 456h

C123h, F456h

—

Memory

55h

0Eh

03h

EFh

00h

F0h

23h

C1h

56h

F4h

Address

000007h

000008h

000009h

00000Ah

00000Bh

00000Ch

00000Dh

00000Eh

00000Fh

000010h

000011h

000012h

DS30475A-page 46

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 2000 Microchip Technology Inc.

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