PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

4.9 Data Memory Organization

The data memory is implemented as static RAM. Each

register in the data memory has a 12-bit address,

allowing up to 4096 bytes of data memory. Figure 4-4

shows the data memory organization for the

PIC18CXX8 devices.

The data memory map is divided into as many as 16

banks that contain 256 bytes each. The lower 4 bits of

the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

The data memory contains Special Function Registers

(SFR) and General Purpose Registers (GPR). The

SFR’s are used for control and status of the controller

and peripheral functions, while GPR’s are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFR’s start at the last location of Bank 15

(0xFFF) and grow downwards. GPR’s start at the first

location of Bank 0 and grow upwards. Any read of an

unimplemented location will read as ’0’s.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of

the File Select Register (FSR). Each FSR holds a

12-bit address value that can be used to access any

location in the Data Memory map without banking.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFF instruction. The

MOVFF instruction is a two word/two cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFR’s and

select GPR’s) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 4.10 pro-

vides a detailed description of the Access RAM.

4.9.1 GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly or indi-

rectly. Indirect addressing operates through the File

Select Registers (FSR). The operation of indirect

addressing is shown in Section 4.12.

Enhanced MCU devices may have banked memory in

the GPR area. GPR’s are not initialized by a Power-on

Reset and are unchanged on all other RESETS.

Data RAM is available for use as GPR registers by all

instructions. Bank 15 (0xF00 to 0xFFF) contains

SFR’s. All other banks of data memory contain GPR

registers starting with bank 0.

4.9.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFR’s) are registers

used by the CPU and Peripheral Modules for control-

ling the desired operation of the device. These regis-

ters are implemented as static RAM. A list of these

registers is given in Table 4-2.

The SFR’s can be classified into two sets: those asso-

ciated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described in this section, while those related

to the operation of the peripheral features are

described in the section of that peripheral feature.

The SFR’s are typically distributed among the peripher-

als whose functions they control.

The unused SFR locations will be unimplemented and

read as '0's. See Table 4-2 for addresses for the SFR’s.

DS30475A-page 48

Advanced Information

 2000 Microchip Technology Inc.

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