PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF8410-I/PTQTP Datasheet PDF : 404 Pages
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PIC18F6310/6410/8310/8410
TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
TQFP
Type Type
Description
PORTG is a bidirectional I/O port.
RG0/CCP3
RG0
CCP3
5
I/O ST
Digital I/O.
I/O ST
Capture 3 input/Compare 3 output/PWM 3 output.
RG1/TX2/CK2
RG1
TX2
CK2
6
I/O ST
Digital I/O.
O
—
AUSART2 asynchronous transmit.
I/O ST
AUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
RX2
DT2
7
I/O ST
Digital I/O.
I
ST
AUSART2 asynchronous receive.
I/O ST
AUSART2 synchronous data (see related TX2/CK2).
RG3
8
I/O ST
Digital I/O.
RG4
10
I/O ST
Digital I/O.
RG5
See RG5/MCLR/VPP pin.
PORTH is a bidirectional I/O port.
RH0/AD16
RH0
AD16
79
I/O ST
Digital I/O.
I/O TTL
External memory address/data 16.
RH1/AD17
RH1
AD17
80
I/O ST
Digital I/O.
I/O TTL
External memory address/data 17.
RH2/AD18
RH2
AD18
1
I/O ST
Digital I/O.
I/O TTL
External memory address/data 18.
RH3/AD19
RH3
AD19
2
I/O ST
Digital I/O.
I/O TTL
External memory address/data 19.
RH4
22
I/O ST
Digital I/O.
RH5
21
I/O ST
Digital I/O.
RH6
20
I/O ST
Digital I/O.
RH7
19
I/O ST
Digital I/O.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for CCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 27
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