PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF8410-I/PTQTP Datasheet PDF : 404 Pages
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PIC18F6310/6410/8310/8410
TABLE 1-3: PIC18F8310/8410 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin Buffer
TQFP
Type Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O ST
Digital I/O.
O
—
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O ST
Digital I/O.
O
—
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O ST
Digital I/O.
O
—
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O ST
Digital I/O.
O
—
External memory write high control.
RJ4/BA0
RJ4
BA0
39
I/O ST
Digital I/O.
O
—
External memory Byte Address 0 control.
RJ5/CE
RJ4
CE
40
I/O ST
Digital I/O
O
—
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O ST
Digital I/O.
O
—
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O ST
Digital I/O.
O
—
External memory high byte control.
VSS
11, 31, 51, 70 P
— Ground reference for logic and I/O pins.
VDD
12, 32, 48, 71 P
— Positive supply for logic and I/O pins.
AVSS
26
P
— Ground reference for analog modules.
AVDD
25
P
— Positive supply for analog modules.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for CCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only).
DS39635A-page 28
Preliminary
2004 Microchip Technology Inc.
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