PSD501B1-C-90UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD501B1-C-90UI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD5XX Family

Counter/Timer

Registers

(Cont.)

Table 23a. Offset Address Map of Counter/Timer-Unit Registers

(For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 23.)

Address

Offset

Register Name

Address

Offset

Register Name

+A8h

STATUS FLAGS

+A9h

GLOBAL COMMAND

+A7h

DLCY

+A4h

SOFTWARE LOAD/STORE

+A5h

FREEZE COMMAND

+A2h

CMD3

+A3h

CMD2

+A0h

CMD1

+A1h

CMD0

+9Eh

CNTR3

+9Fh

CNTR3

+9Ch

CNTR2

+9Dh

CNTR2

+9Ah

CNTR1

+9Bh

CNTR1

+98h

CNTR0

+99h

CNTR0

+96h

IMG3

+97h

IMG3

+94h

IMG2

+95h

IMG2

+92h

IMG1

+93h

IMG1

+90h

IMG0

+91h

IMG0

Registers IMG0 through IMG3 are written to by the microcontroller to load the

Counter/Timers with required values in Waveform, Pulse and WatchDog mode only.

To retrieve the count or time in Event count or Time capture modes, Counter/Timers store

their values into IMG0 through IMG3.

Any access to the Image Registers must conform to the Freeze/Freeze Acknowledge

protocol, described later in the Freeze Command paragraph.

82

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