PSD501B1-C-90UI View Datasheet(PDF) - STMicroelectronics
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Description
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PSD501B1-C-90UI Datasheet PDF : 153 Pages
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Counter / Timer
Registers
(Cont.)
PSD5XX Family
9.6.2.3 Configuring the Mode of Operation of the Counter/Timers:
Using the GLOBAL MODE bit of the Global Command register and MODE SELECT bit of
the Command register of Counter/Timers 0 – 3, individual Counter/Timer modes of operation
can be set up. Refer to Table 24. Notice that all the Counter/Timers can either operate in
Waveform/Pulse or Event Count/Time Capture modes, but not in all four modes at the same
time.
Table 24. Counter/Timer Modes
Global Mode Bit
(Global Command
Register)
Mode Select Bit
( Command
Registers of
Counter/Timers
0 – 3 CMD0, CMD1,
CMD2 and CMD3)
0
0
0
1
1
0
1
1
Modes
of
Counter/Timers
0, 1 and 3
Modes
of
Counter/Timer2
Waveform
Pulse
Event Counter
Time Capture
Waveform or
WatchDog
Pulse or
WatchDog
WatchDog Only
WatchDog Only
9.6.2.4 Freeze Command Register
When a Microcontroller needs to access the contents of the Image Registers (IMG0-IMG3)
it does so by first setting the Command Register Freeze bit in order to disable the timer
state-machine accesses of the Image Register. The Microcontroller waits for the Freeze
Acknowledge bit in the Counter/Timer Status Register to be set to 1 and then it accesses
the Image Register as an address location. The freeze acknowledge signal effectively guar-
antees stable Image Register data during Microcontroller read/write cycles even though the
Counter/Timer continues to count. The Freeze Acknowledge bit gets cleared after the
negation of Freeze. The Freeze Command bits are set and cleared by the microcontroller
software.
The Freeze Command Register and the software Load/Store Register should not be set at
the same time. It is recommended that the registers be accessed individually.
Bit 7
Bit 6
*
*
NOTE: * = Not used.
Bit 5
*
Bit 4
*
Bit 3
Freeze
CTU3
Bit 2
Freeze
CTU2
Bit 1
Freeze
CTU1
Bit 0
Freeze
CTU0
87
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