PSD834F2V
Table 36. Example of PSD Typical Power Calculation at VCC = 3.3 V (with Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD)
= 8 MHz
MCU ALE frequency (Freq ALE)
= 4 MHz
% Flash memory
Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode
= Off
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.5 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 25 µA x 0.90 + 0.1 x (0.8 x 1.5 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 14 mA)
= 22.5 µA + 0.1 x (4.8 + 0.48 + 14) mA
= 22.5 µA + 0.1 x 19.28 mA
= 22.5 µA + 1.928 mA
= 1.95 mA
This is the operating power with no Write or Flash memory Erase cycles in progress.
Calculation is based on IOUT = 0 mA.
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