PSD934210MT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD934210MT

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

Table 43. CPLD Combinatorial Timing

Symbol

Parameter

Conditions

-10

-15

Min Max Min Max

-20

Min Max

PT

Aloc

Turbo Slew

Off rate1

Unit

CPLD Input Pin/

tPD

Feedback to CPLD

Combinatorial Output

40

45

50 + 4 + 20 – 6 ns

tEA

CPLD Input to CPLD

Output Enable

43

45

50

+ 20 – 6 ns

tER

CPLD Input to CPLD

Output Disable

43

45

50

+ 20 – 6 ns

CPLD Register Clear

tARP

or

Preset Delay

40

43

48

+ 20 – 6 ns

tARPW

CPLD Register Clear

or

Preset Pulse Width

25

30

35

+ 20

ns

tARD

CPLD Array Delay

Any

macrocell

25

29

33 + 4

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

Table 44. CPLD Macrocell Synchronous Clock Mode Timing

Symbol

Parameter

Conditions

-10

Min Max

-15

-20

Min Max Min Max

PT

Aloc

Turbo Slew

Off rate1

Unit

Maximum

Frequency

External Feedback

1/(tS+tCO)

22.2

18.8

15.8

MHz

fMAX

Maximum

Frequency

Internal Feedback

(fCNT)

1/(tS+tCO–10)

28.5

23.2

18.8

MHz

Maximum

Frequency

Pipelined Data

1/(tCH+tCL)

40.0

33.3

31.2

MHz

tS

Input Setup Time

20

25

30

+ 4 + 20

ns

tH

Input Hold Time

0

0

0

ns

tCH

Clock High Time

Clock Input 15

15

16

ns

tCL

Clock Low Time

Clock Input 10

15

16

ns

tCO

Clock to Output

Delay

Clock Input

25

28

33

– 6 ns

tARD

CPLD Array Delay Any macrocell

25

29

33 + 4

ns

Minimum Clock

tMIN

Period2

tCH+tCL

25

29

32

ns

Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.

2. CLKIN (PD1) tCLCL = tCH + tCL .

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