SI3201-X-FS View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
SI3201-X-FS
Silicon Laboratories
SI3201-X-FS Datasheet PDF : 100 Pages
| |||
Si3233
Register 107. DC Peak Current Monitor Calibration Result
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CMDCPK[3:0]
Type
R/W
Reset settings = 0000_1000
Bit
Name
Function
7:4
Reserved Read returns zero.
3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result.
Register 108. Enhancement Enable
Bit
D7
D6
D5
D4
Name ILIMEN FSKEN DCSU
Type R/W
R/W
R/W
Reset settings = 0000_0000
D3
D2
D1
D0
LCVE DCFIL HYSTEN
R/W
R/W
R/W
Bit
Name
Function
7
ILIMEN
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
6
FSKEN
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 16 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 16 kHz.
5
DCSU
DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
4:3 Reserved Read returns zero.
Preliminary Rev. 0.5
83
Share Link: 