SI3201-X-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3201-X-FS

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3233

4. Indirect Registers

Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A

write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the

contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.

A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the

value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of

16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an

interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.

Si3230

Indirect

Register

13

14

15

16

17

18

19

20

21

22

26

Table 30. Si3230 to Si3233 Indirect Register Cross Reference

Si3233

Indirect

Register

0

1

2

3

4

5

6

7

8

9

13

Indirect

Register

Name

OSC1

OSC1X

OSC1Y

OSC2

OSC2X

OSC2Y

ROFF

RCO

RNGX

RNGY

DACG

Si3230

Indirect

Register

27

28

29

30

31

32

33

34

35

36

37

Si3233

Indirect

Register

14

15

16

17

18

19

20

21

22

23

24

Indirect

Register

Name

ADCG

LCRT

RPTP

CML

CMH

PPT12

PPT34

PPT56

NCLR

NRTP

NQ12

Si3230

Indirect

Register

38

39

40

41

43

99

100

101

102

103

104

Si3233

Indirect

Register

25

26

27

64

66

69

70

71

72

73

74

Indirect

Register

Name

NQ34

NQ56

VCMR

VMIND

LCRTL

FSK0X

FSK0

FSK1X

FSK1

FSK01

FSK10

All values are represented in twos-complement format.

Note: The values of all indirect registers are undefined following the reset state.

4.1. Oscillators

See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing

register values. All values are represented in twos-complement format.

Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read

and written but should be written to zeroes.

Table 31. Oscillator Indirect Registers Summary

Addr D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

OSC1[15:0]

1

OSC1X[15:0]

2

OSC1Y[15:0]

3

OSC2[15:0]

4

OSC2X[15:0]

5

OSC2Y[15:0]

6

ROFF[5:0]

Preliminary Rev. 0.5

85

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