SI3201-X-FS View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3201-X-FS

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3233

Table 36. SLIC Control Indirect Registers Description (Continued)

Addr

20

21

22

23

24

25

26

27

64

66

Description

Power Alarm Threshold for Transistors Q3 and Q4.

Power Alarm Threshold for Transistors Q5 and Q6.

Loop Closure Filter Coefficient.

Ring Trip Filter Coefficient.

Thermal Low Pass Filter Pole for Transistors Q1 and Q2.

Thermal Low Pass Filter Pole for Transistors Q3 and Q4.

Thermal Low Pass Filter Pole for Transistors Q5 and Q6.

Common Mode Bias Adjust During Ringing.

Recommended value of 0 decimal.

DC-DC Converter VOV Voltage (Si3233 only).

This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV

bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the

VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h).

Loop Closure Threshold—Lower Bound.

This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of

direct Register 108. The range is 0–80 mA in 1.27 mA steps.

4.4. FK Control

For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These

registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,

bit 6) and REL = 1 (direct Register 32, bit 6).

Table 37. FSK Control Indirect Registers Summary

Addr D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

69

FSK0X[15:0]

70

FSK0[15:0]

71

FSK1X[15:0]

72

FSK1[15:0]

73

FSK01[15:0]

74

FSK10[15:0]

Preliminary Rev. 0.5

89

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